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16 - bit, 1 msps, pulsar adc in msop/lfcsp data sheet ad7980 rev. f document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. t el: 781.329.4700 ? 2007 C 2017 analog devices, inc. all rights reserved. technical support www.analog.com features 16 - bit resolution with no missing codes throughput: 1 msps low p ower dissipation 4 mw at 1 msps (vdd only) 7 mw at 1 msps ( t otal) 7 0 w at 10 ksps inl: 0.6 lsb typ ical , 1.25 lsb max imum s i n a d: 91. 2 5 db at 1 0 khz thd: ? 1 10 db at 1 0 khz pseudo differential analog input range 0 v to v ref with v ref between 2.5 v to 5 v no pipeline delay single - supply 2.5 v operation with 1.8 v/2.5 v/3 v/5 v logic interface proprietary s erial interface spi/qspi/microwire?/ dsp compatible daisy - chain multiple adcs and busy indicator 10 - lead msop and 10- lead, 3 mm 3 mm lfcsp, same space as sot - 23 wide operating temperature range: ? 40c to +125c applications battery - powered equipment communications automatic test equipment ( ate ) data acquisitions medical instruments typical application circuit figure 1. general description the ad7980 1 is a 16 - bit, successive approximation, analog - to - digital conver ter (adc) that operates from a single power supply, vdd. it contains a low power, high speed, 16 - bit sampling adc and a versatile serial interface port. on the cnv rising edge, it samples an analog input , i n+ , between 0 v to ref with respect to a ground sense , in?. the reference voltage, ref, is applied externally and can be set independent of the supply voltage, vdd. its power scales linearly with throughput. the spi - compatible serial interface also feature s the ability , using the sdi input, to daisy - chain several adcs on a single, 3 - wire bus and provides an optional busy indicator. it is compatible with 1.8 v, 2.5 v, 3 v, or 5 v logic, using the separate supply vio. the ad7980 is housed in a 10 - lead msop or a 10 - lead lfcsp with operation specified from ? 40c to + 12 5c. 1 protected by u.s. patent 6,703,961. table 1 . msop, lfcsp 14 - /16- /18 - /20- bit p recision sar adc s and integrated sar adc module s type 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps module data acquisition system 20 - bit ad4020 1 18 - bit ad7989 -1 1 ad7691 1 ad4011 1 ad4003 1 ad7690 1 ad4007 1 ad7989 -5 1 ad7982 1 ad7984 1 16 - bit ad7680 ad768 5 1 ad7686 1 ad4001 1 adaq7980 ad7683 ad7687 1 ad7688 1 ad4005 1 adaq7988 ad7684 ad7694 ad7693 1 ad4000 1 ad7988 -1 1 ad7988 -5 1 ad4004 1 ad7916 1 ad7980 1 ad4008 1 ad7983 1 14 - bit ad7940 ad7942 1 ad7946 1 1 pin for pin compatible. 06392-001 ad7980 ref gnd vdd in+ inC vio sdi sck sdo cnv 1.8v t o 5.0v 3- or 4-wire inter f ace (spi, dais y chain, cs) 2.5v t o 5v 2.5v 0 t o vref
ad7980* product page quick links last content update: 11/02/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? ad7980 evaluation kit ? precision adc pmod compatible boards documentation application notes ? an-742: frequency domain response of switched- capacitor adcs ? an-931: understanding pulsar adc support circuitry ? an-932: power supply sequencing data sheet ? ad7980-dscc: military data sheet ? ad7980-ep: enhanced product data sheet ? ad7980: 16-bit, 1 msps, pulsar adc in msop/lfcsp data sheet product highlight ? [no title found] product highlight ? lowest-power 16-bit adc optimizes portable designs (eeproductcenter, 10/4/2006) user guides ? ug-340: evaluation board for the 10-lead family 14-/16-/ 18-bit pulsar adcs ? ug-682: 6-lead sot-23 adc driver for the 8-/10-lead family of 14-/16-/18-bit pulsar adc evaluation boards software and systems requirements ? ad7980 - no-os driver for microchip microcontroller platforms ? ad7980 - no-os driver for renesas microcontroller platforms ? ad7980 fmc-sdp interposer & evaluation board / xilinx kc705 reference design ? bemicro fpga project for ad7980 with nios driver tools and simulations ? ad7980 ibis models reference materials press ? analog devices to host name that beer demonstration using spectrometer technology from wasatch photonics at electronica 2012 ? most power efficient drivers for 12-, 14- and 16-bit a/d converters unveiled product selection guide ? sar adc & driver quick-match guide technical articles ? explaining sar adc power specifications ? exploring different sar adc analog input architectures ? introduction to dynamic power scaling ? ms-1779: nine often overlooked adc specifications ? ms-2210: designing power supplies for high speed adc ? powering a precision sar adc using a high efficiency, ultralow power switcher in power sensitive applications tutorials ? mt-001: taking the mystery out of the infamous formula, "snr=6.02n + 1.76db", and why you should care ? mt-002: what the nyquist criterion means to your sampled data system design ? mt-031: grounding data converters and solving the mystery of "agnd" and "dgnd" design resources ? ad7980 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad7980 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number.
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ad7980 data sheet rev. f | page 2 of 26 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuit ............................................................. 1 general description ......................................................................... 1 revision h istory ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 terminology ...................................................................................... 9 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 14 ci rcuit information .................................................................... 14 converter operation .................................................................. 14 typical application circuit with multiple supplies ............... 15 analog input ............................................................................... 16 driver amplifier choice ........................................................... 16 voltage reference input ............................................................ 17 power supply ............................................................................... 17 digital interface .......................................................................... 17 3 - wire cs mode without busy indicator .............................. 18 3 - wire cs mode with busy indicator ..................................... 19 4 - wire cs mode without busy indicator .............................. 20 4 - wire cs mode with busy indicator ..................................... 21 chain mode without busy indicator ...................................... 22 chain mode with busy indicator ............................................. 23 applications information .............................................................. 24 layout .......................................................................................... 24 evaluating the performance of the ad7980 .............................. 24 outline dimensions ....................................................................... 25 ordering g uide .......................................................................... 26 revision history 10/2017 rev. e to rev. f changes to table 1 ............................................................................ 1 changes to figure 5 .......................................................................... 8 updated outline dimensions ....................................................... 26 changes to ordering guide .......................................................... 26 7 /2016 rev. d to rev. e changed vio = 2.3 v to 5.5 v to vi o = 1.71 v to 5.5 v ................................................................................. throughout change to features section ............................................................. 1 changes to conversion rate parameter, table 2 .......................... 3 changes to vio parameter, table 3 ............................................... 4 d eleted vio range parameter, table 3 ......................................... 4 added table 5 ; renumbered sequentially .................................... 6 changes to table 7 ............................................................................ 8 changes to table 9 .......................................................................... 16 change s to voltage reference input section .............................. 17 changes to figure 32 ...................................................................... 18 changes to figure 34 ...................................................................... 19 changes to figure 3 6 ...................................................................... 20 changes to figure 38 ...................................................................... 21 changes to figure 40 ...................................................................... 22 changes to figure 42 ...................................................................... 23 7 / 20 14 rev. c to rev. d changed qfn (lfcsp) to lfcsp .............................. throughout changes to features section and table 1 ...................................... 1 added patent n ote , note 1 .............................................................. 1 changes to ac accuracy parameter, table 2 ................................ 3 change to standby current parameter, table 3 ............................ 4 change s to figure 25 ...................................................................... 13 changes to table 8 .......................................................................... 15 changes to power supply section ................................................ 16 8 / 20 13 rev. b to rev. c change to features section .............................................................. 1 changes to table 3 ............................................................................. 4 change to figure 5 ............................................................................ 7 added epad row, table 6 ............................................................... 7 changes to evaluating the performance of the ad 7980 section .............................................................................. 23 updated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 25 6 / 20 09 rev. a to rev. b changes to table 5 ............................................................................. 6 changes to figure 25 ...................................................................... 13 updated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 25 9 / 20 08 rev. 0 to rev. a delete d qfn endnote .................................................. throughout changes to ordering guide .......................................................... 24 8 / 20 07 revision 0: initial version
data sheet ad7980 rev. f | page 3 of 26 specifications vdd = 2.5 v, vio = 1.71 v to 5.5 v, v ref = 5 v, t a = ? 40c to + 12 5c, unless otherwise noted. table 2 . a grade b grade parameter test conditions /comments min typ max min typ max unit resolution 16 16 bits analog input voltage range in+ ? in? 0 v ref 0 v ref v absolute input voltage in+ ?0.1 v ref + 0.1 ?0.1 v ref + 0.1 v in? ?0.1 +0.1 ?0.1 +0.1 v analog input cmrr f in = 1 00 k hz 6 0 6 0 db leakage current at 25c acquisition phase 1 1 na input impedance see the analog input section see the analog input section accuracy no missing codes 16 16 bits differential linearity error ref = 5 v ? 1.0 0 . 5 +2.0 ? 0.9 0. 4 + 0.9 lsb 1 ref = 2.5 v 0.7 0.55 lsb 1 integral linearity error ref = 5 v ?2.5 1.5 +2.5 ?1.25 0.6 +1.25 lsb 1 ref = 2.5 v 1.65 0.65 lsb 1 transition noise ref = 5 v 0.75 0.6 lsb 1 ref = 2.5 v 1.2 1.0 lsb 1 gain error, t min to t max 2 2 2 lsb 1 gain error temperature drift 0.35 0.35 ppm/c zero error, t min to t max 2 ?1.0 0. 08 +1.0 ?0.5 0.08 +0.5 mv zero temperature drift 0.54 0.54 ppm/c power supply sensitivity vdd = 2.5 v
ad7980 data sheet rev. f | page 4 of 26 vdd = 2.5 v, vio = 1.71 v to 5.5 v, v ref = 5 v, t a = ? 40c to + 12 5c, unless otherwise noted. table 3 . parameter test conditions/comments min typ max unit reference voltage range 2. 4 5. 1 v load current 1 msps, ref = 5 v 330 a sampling dynamics ?3 db input bandwidth 10 mhz aperture delay vdd = 2.5 v 2. 0 ns digital inputs logic levels v il vio > 3v C 0.3 0.3 vio v v ih vio > 3v 0.7 vio vio + 0.3 v v il vio 3v C 0.3 0.1 vio v ih vio 3v 0.9 vio vio + 0.3 a i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial 16 bits straight binary pipeline delay conversion results available immediately after completed conversion v ol i sink = 500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd 2.375 2.5 2.625 v vio 1.71 5.5 v standby current 1 , 2 vdd and vio = 2.5 v, 25c 0.35 a power dissipation vdd = 2.62 5 v, v ref = 5 v, vio = 3 v total 10 ksps throughput 70 w 1 msps throughput, b g rade 7.0 9.0 mw 1 msps throughput, a g rade 7.0 10 mw vdd only 4 mw ref only 1.7 mw vio only 1.3 mw energy per conversion 7.0 nj/sample temperature range 3 specified performance t min to t max ?40 +125 c 1 with all digital inputs forced to vio or gnd as required. 2 during the acquisition phase. 3 contact sales for extended temperature ra nge.
data sheet ad7980 rev. f | page 5 of 26 timing specification s ?40c to + 12 5c, vdd = 2.37 v to 2.63 v, vio = 3 .3 v to 5.5 v, unless otherwise stated. see figure 2 and figure 3 for load conditions. table 4 . parame ter symbol min typ max unit conversion time: cnv rising edge to data available t conv 500 710 ns acquisition time t acq 290 ns time between conversions t cyc 1000 ns cnv pulse width ( cs mode) t cnvh 10 ns sck period ( cs mode) t sck ns vio above 4.5 v 10.5 ns vio above 3 v 12 ns vio above 2.7 v 13 ns vio above 2.3 v 15 ns sck period (chain mode) t sck ns vio above 4.5 v 11.5 ns vio above 3 v 13 ns vio above 2.7 v 14 ns vio above 2.3 v 16 ns sck low time t sckl 4.5 ns sck high time t sckh 4.5 ns sck falling edge to data remains valid t hsdo 3 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 9.5 ns vio above 3 v 11 ns vio above 2.7 v 12 ns vio above 2.3 v 14 ns cnv or sdi low to sdo d15 msb valid ( cs mode) t en vio above 3 v 10 ns vio above 2.3 v 15 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 20 ns sdi valid setup time from cnv rising edge t ssdicnv 5 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 2 ns sdi valid hold time from cnv rising edge (chain mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 5 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 2 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 3 ns sdi high to sdo high (chain mode with busy indicator) t dsdosdi 15 ns
ad7980 data sheet rev. f | page 6 of 26 ?40 c to +125c , vdd = 2.37 v to 2.6 3 v, vio = 1.71 v to 3.3 v, unless otherwise stated. see figure 2 and figure 3 for load conditions. table 5 . parameter symbol min typ max unit throughput rate 833 ksps conversion time: cnv rising edge to data available t conv 500 800 ns acquisition time t acq 290 ns time between conversions t cyc 1.2 s cnv pulse width ( cs mode) t cnvh 10 ns sck period ( cs mode) t sck 22 ns sck period (chain mode) t sck 23 ns sck low time t sckl 6 ns sck high time t sckh 6 ns sck falling edge to data remains valid t hsdo 3 ns sck falling edge to data valid delay t dsdo 14 21 ns cnv or sdi low to sdo d15 msb valid ( cs mode) t en 18 40 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 20 ns sdi valid setup time from cnv rising edge t ssdicnv 5 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 10 ns sdi valid hold time from cnv rising edge (chain mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 5 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 2 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 3 n s sdi high to sdo high (chain mode with busy indicator) t dsdosdi 22 ns timing diagrams figure oa ircuit for digita nterface timing figure otage ees for timing 500 a i ol 500 a i oh 1.4v t o sdo c l 20pf 06513-002 06392-003 x% vio 1 y% vio 1 v ih 2 v il 2 v il 2 v ih 2 t delay t delay 1 for vio 3.0v, x = 90 and y = 10; for vio > 3.0v x = 70, and y = 30. 2 minimum v ih and maximum v il used. see digital inputs specifications in table 3.
data sheet ad7980 rev. f | page 7 of 26 absolute maximum rat ings table 6 . parameter rating analog inputs in+ , 1 in? 1 to gnd ?0.3 v to v ref + 0.3 v or 130 ma supply voltage ref, vio to gnd ?0.3 v to + 6 v vdd to gnd ?0.3 v to +3 v vdd to vio + 3 v to ? 6 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c thermal impedance (10 - lead msop) ja 200c/w jc 44c/w lead temperature vapor phase (60 sec) 215c infrared (15 sec) 220c 1 see the analog input section. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution
ad7980 data sheet rev. f | page 8 of 26 pin configuration s and function descrip tions figure 4 . 10 - lead msop pin configuration figure 5 . 10 - lead lfcsp pin configuration table 7 . pin function descriptions pin no. mnemonic type 1 description msop lfcsp 1 1 ref ai reference input voltage. the ref range is from 2.4 v to 5.1 v. it is referred to the gnd pin. this pin should be decoupled closely to the pin with a 10 f capacitor. 2 2 vdd p power supply. 3 3 in+ ai analog input. it is referred to in ? . the voltage range, for example, the difference between in+ and in?, is 0 v to v ref . 4 4 in ? ai analog input ground sense. to be connected to the analog ground plane or to a remote sense ground. 5 5 gnd p power supply ground. 6 6 cnv di convert inpu t. this input has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode of the device , chain, or cs mode. in cs mode, it enables the s do pin when low. in chain mode, the data should be read when cnv is high. 7 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 8 sck di serial data clock input. when the device is selected, the conversion result is shifted out by this clock. 9 9 sdi di serial data input. this input provides multiple features. it selects the interface mode of the adc as follows. chain mode is selected if sdi is low during the cnv rising edge. in this mode, sdi is used as a data input to daisy - chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 16 sck cycles. cs mode is selected if sdi is high during the cnv rising edge. in this mode, either sdi or cnv can enable the serial output signals when low; if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. 10 10 vio p input/outp ut interface digital power. nominally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). not a pplicable 0 epad not applicable exposed pad. c onnect the exposed pad to gnd. this connection is not required to meet the electrical performances. 1 ai = analog input, di = digital input, do = digital output, and p = power. 06392-004 ref 1 vdd 2 in+ 3 inC 4 vio 10 sdi 9 sck 8 sdo 7 gnd 5 cnv 6 ad7980 t o p view (not to scale) 1 ref 2 vdd 3 in+ 4 inC 5 gnd 10 vio 9 sdi 8 sck 7 sdo 6 cnv 06392-005 ad7980 t op view (not to scale) notes 1. connect the exposed p ad t o gnd. this connection is not required t o meet the electrica l performances.
data sheet ad7980 rev. f | page 9 of 26 terminology integral nonlinearity error (inl) i nl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point use d as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line ( see figure 26). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. offset error the first transition should occur at a level ? lsb above analog ground (38.1 v for the 0 v to 5 v range). the offset error is the deviation of the actual transition from that point. gai n error the last transition (from 111 10 to 111 11) should occur for an analog voltage 1? lsb below the nominal full scale (4.999886 v for the 0 v to 5 v range). the gain error is the deviation of the actual level of the last transition from the ideal level after the offset is adjusted out. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is expressed in bits and related to sinad by the following formula : enob = ( sinad db ? 1.76)/6.02 noise - free code re solution noise - free code resolution is the number of bits beyond which it is impossible to distinctly r esolve individual codes. it is calculated as noise - free code r esolution = log 2 (2 n / peak - to - peak noise ) and is expressed in bits. effective r esolution effective resolution is calculated as effective r esolution = log 2 (2 n / rms input no ise) and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in db. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. the value for dynamic range is expressed in db. it is measured with a signal at ? 60 dbf s to include all noise sources and dnl artifacts. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in db. signal -to - noise - and - distortion ratio (s i n a d) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in db. aperture delay aperture delay is t he measur e of the acquisition performance . i t is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient response t ransient response is t he time required for the adc to accurately acquire its input after a ful l - scale step function i s applied .
ad7980 data sheet rev. f | page 10 of 26 typical performance characteristics vdd = 2.5 v, v ref = 5.0 v, vio = 3.3 v, unless otherwise noted. figure 6. integral nonlinearity vs. code, ref = 5 v figure 7. integral nonlinearity vs. code, ref = 2.5 v figure 8. fft plot, ref = 5 v figure 9. differential nonlinearity vs. code, ref = 5 v figure 10. differential nonlinearity vs. code, ref = 2.5 v figure 11. fft plot, ref = 2.5 v 1.25 ?1.25 0 65536 06392-036 code inl (lsb) 1.00 0.75 0.50 0.25 ?0.25 ?0.75 0 ?0.50 ?1.00 16384 32768 49152 positive inl: +0.33 lsb negative inl: ?0.39 lsb 1.25 1.00 ?1.25 ?1.00 0 65536 06392-060 code inl (lsb) 0.75 0.50 0.25 ?0.25 ?0.75 0 ?0.50 16384 32768 49152 positive inl: +0.47 lsb negative inl: ?0.26 lsb 0 ?180 0500 06392-038 frequency (khz) amplitude (db of full scale) ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 100 200 300 400 f s = 1 msps f in = 10khz snr = 91.27db thd = ?114.63db sfdr = 110.10db sinad = 91.25db 1.00 ?1.00 0 65536 06392-039 code dnl (lsb) 0.75 0.50 0.25 ?0.25 ?0.75 0 ?0.50 16384 32768 49152 positive inl: +0.18 lsb negative inl: ?0.21 lsb 1.00 ?1.00 0 65536 06392-061 code dnl (lsb) 0.75 0.50 0.25 ?0.25 ?0.75 0 ?0.50 16384 32768 49152 positive inl: +0.25 lsb negative inl: ?0.22 lsb 0 ?180 0500 06392-058 frequency (khz) amplitude (db of full scale) ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 100 200 300 400 f s = 1 msps f in = 10khz snr = 86.8db thd = ?111.4db sfdr = 105.9db sinad = 86.8db
data sheet ad7980 rev. f | page 11 of 26 figure 12. histogram of a dc input at the code center, ref = 5 v figure 13. histogram of a dc input at the code transition, ref = 5 v figure 14. snr, sinad, and enob vs. reference voltage figure 15. histogram of a dc input at the code center, ref = 2.5 v figure 16. snr vs. input level figure 17. thd, sfdr vs. reference voltage 180k 0 800c 800d 800e 800f 80098008 800b 800a 8003 80058004 80078006 2000 33 829 0 27 0 1201 06392-042 code in hex counts 140k 160k 100k 120k 60k 20k 80k 40k 38751 168591 52710 70k 0 7fff 8008 8001 8000 8003 8002 8005 8004 8007 8006 0 0 150 2 59691 5428 59404 3 93 06392-043 code in hex counts 60k 50k 30k 10k 40k 20k 6295 100 80 85 90 95 2.25 5.25 06392-044 reference voltage (v) snr, sinad (db) 16 12 13 14 15 enob (bits) 2.75 3.25 3.75 4.25 4.75 snr sinad enob 60k 0 7ffa 8006 7ffc 7ffb 7ffe 7fff 7ffd 80018000 8003 8004 8005 8002 00 0 0 539 16 14 502 06392-059 code in hex counts 50k 30k 10k 40k 20k 32417 52212 31340 7225 6807 95 85 87 89 92 91 93 94 86 88 90 ?10 0 06392-046 input level (db of full scale) snr (db) ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 ? 95 ?125 ?110 ?115 ?105 ?100 ?120 115 85 100 95 105 110 90 2.25 5.25 06392-047 reference voltage (v) thd (db) sfdr (db) 2.75 3.25 3.75 4.25 4.75 thd sfdr
ad7980 data sheet rev. f | page 12 of 26 figure 18. sinad vs. frequency figure 19. snr vs. temperature figure 20. operating currents vs. supply figure 21. thd vs. frequency figure 22. thd vs. temperature figure 23. operating currents vs. temperature 100 80 10 1000 06392-063 frequency (khz) sinad (db) 95 90 85 100 95 85 89 87 91 93 ?55 125 06392-049 temperature (c) snr (db) ?35 ?15 5 25 65 85 45 105 06392-050 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 current (ma) 2.425 2.475 vdd voltage (v) 2.375 2.525 2.575 2.625 i vdd i ref i vio ? 85 ?125 10 1000 06392-064 frequency (khz) thd (db) 100 ?90 ?95 ?100 ?105 ?110 ?115 ?120 06392-052 ? 110 ?120 thd (db) ?55 ?35 ?15 5 25 temperature (c) 45 65 85 105 125 ?112 ?114 ?116 ?118 06392-053 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 current (ma) ?55 ?35 ?15 5 25 temperature (c) 45 65 85 105 125 i vdd i ref i vio
data sheet ad7980 rev. f | page 13 of 26 figure 24 . power - down currents vs. temperature 06392-054 8 7 6 5 4 3 2 1 0 current (a) C55 C35 C15 5 25 temper a ture (c) 45 65 85 105 125 i vdd + i vio
ad7980 data sheet rev. f | page 14 of 26 theory of operation figure 25 . adc simplified schematic circuit information the ad7980 is a fast, low power, single - supply, precise 16 - bit adc that us es a successive approximation architecture. the ad7980 is capable of converting 1,000,000 samples per second (1 msps) and powers down between conversions. when operating at 10 ksps, for example, it consumes 7 0 w typically, ideal for battery - powered applications. the ad7980 provides the user with on - chip track - and - hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. the ad7980 can be interfaced to any 1.8 v to 5 v digital logic family. it is housed in a 10 - lead msop or a tiny 10 - lead lfcsp that combines space savings and allows flexible configurations. it is pin - for - pin compatible with the 18 - bit ad7982 . converter operation the ad7980 is a successive approximation adc based on a charge redistribution dac. figure 25 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to t he input of the comparator are connected to gnd via sw+ and sw?. all i ndependent switches are connected to the analog inputs . th erefore , the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs. when the acquisition phase is complete d and the cnv i nput goes high, a conversion phase is initiated. when the conversion phase begins , sw+ and sw? are opened first. the two capacitor arrays are then dis connected from the inputs and connected to the gnd input. therefore, the differential voltage between the inputs in+ and in? captured at the end of the acquisition phase are applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref, the comparator input varies by binary weight ed voltage steps (v ref /2, v ref /4 v ref /65 , 536). the contro l logic toggles these switches, starting with the msb, to bring the comparator back i n to a balanced condition. after the completion of this process, the device returns to the acquisition phase and the control logic generates the adc output code and a busy signal indicator. because the ad7980 has an on - board conversion clock, the serial clock, sck, is not required for the conversion process. 06392-0 1 1 com p switches contro l bus y output code cnv contro l logic sw+ lsb sw+ lsb in+ ref gnd inC msb msb c c 4c 2c 16,384c 32,768c c c 4c 2c 16,384c 32,768c
data sheet ad7980 rev. f | page 15 of 26 transfer functions the ideal transfer characteristic for the ad7980 is shown in figure 26 and table 8 . figure 26 . adc ideal transfer function table 8 . output codes and ideal input voltages analog input description v ref 5 v digital output code ( he ) fsr ? 1 lsb 4.999924 v ffff 1 midscale + 1 lsb 2.500076 v 8001 midscale 2.5 v 8000 midscale ? 1 lsb 2.499924 v 7fff ? fsr + 1 lsb 76.3 v 0001 ? fsr 0 v 0000 2 1 this is also the code for an overranged analog input (v in+ ? v in? above v ref ? v gnd ). 2 this is also the code for an underranged analog input (v in+ ? v in? below v gnd ). typical application circuit with multiple supplies figure 27 shows an example of a typical application circuit for the ad7980 when multiple supplies are available. figure 27 . typical application circuit with multiple supplies 000 ... 000 000 ... 001 000 ... 010 11 1 ... 101 11 1 ... 1 10 11 1 ... 11 1 Cfsr Cfsr + 1lsb Cfsr + 0.5lsb +fsr C 1 lsb +fsr C 1.5 lsb 06392-012 analog input adc code (straight binary) 06392-013 ad7980 3- or 4-wire inter f ace 2.5v v+ 20 v+ vC 0 t o vref 1.8v t o 5v 100nf 10f 2 2.7nf 4 100nf ref in+ inC vdd vio sdi cnv sck sdo gnd ref 1 1 see the vo lt age reference input section for reference selection. 2 c ref is usual l y a 10f ceramic ca p aci t or (x5r). 3 see the driver amplifier choice section. 4 optiona l fi l ter. see the analog input section. 5 see the digi t a l inter f ace for the most convenient inter f ace mode.
ad7980 data sheet rev. f | page 16 of 26 analog input figure 28 shows an equivalent circuit of the input structure of the ad7980. the two diodes, d1 and d2, provide esd protection for the analog inputs, in+ and in?. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v, because this causes these diodes to become forward- biased and start conducting current. these diodes can handle a forward-biased current of 130 ma maximum. for instance, these conditions could eventually occur when the supplies of the input buffer (u1) are different from vdd. in such a case (for example, an input buffer with a short circuit), the current limitation can be used to protect the device. figure 28. equivalent analog input circuit the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differential inputs, signals common to both inputs are rejected. during the acquisition phase, the impedance of the analog inputs (in+ and in?) can be modeled as a parallel combination of capacitor, c pin , and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 400 and is a lumped component made up of some serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are opened, the input impedance is limited to c pin . r in and c in make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise. when the source impedance of the driving circuit is low, the ad7980 can be driven directly. large source impedances significantly affect the ac performance, especially thd. the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. driver amplifier choice although the ad7980 is easy to drive, the driver amplifier needs to meet the following requirements: ? the noise generated by the driver amplifier needs to be kept as low as possible to preserve the snr and transition noise performance of the ad7980 . the noise coming from the driver is filtered by the 1-pole, low-pass filter of the ad7980 analog input circuit made by r in and c in or by the external filter, if one is used. because the typical noise of the ad7980 is 47.3 v rms, the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 3db 2 )( 2 47.3 47.3 log20 n loss nef snr where: f C3db is the input bandwidth in mhz of the ad7980 (10 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buffer configuration). e n is the equivalent input noise voltage of the op amp, in nv/hz. ? for ac applications, the driver should have a thd performance commensurate with the ad7980. ? for multichannel multiplexed applications, the driver amplifier and the ad7980 analog input circuit must settle for a full-scale step onto the capacitor array at a 16-bit level (0.0015%, 15 ppm). in the amplifier data sheet, settling at 0.1% to 0.01% is more commonly specified. this can differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. table 9. recommended driver amplifiers 1 amplifier typical application ada4805-1 low noise, small size, and low power ada4807-1 very low noise and high frequency ada4627-1 precision, low noise, and low input bias current ada4522-1 precision, zero drift, and emi enhanced ada4500-2 precision, rail-to-rail in put/output, and zero input crossover distortion 1 for the latest recommended drivers, see the product recommendations listed on the product webpage. 06392-014 ref r in c in in+ o r in? gnd d2 c pin d1
data sheet ad7980 rev. f | page 17 of 26 voltage reference input the ad7980 voltage reference input, ref, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the ref and gnd pins, as explained in the layout section. when ref is driven by a very low impedance source, for example, a reference buffer using the ad8031 or the ada4805-1 , a ceramic chip capacitor is appropriate for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference used. for instance, a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift adr435 reference. if desired, a reference-decoupling capacitor value as small as 2.2 f can be used with a minimal impact on performance, especially dnl. regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and gnd pins. power supply the ad7980 uses two power supply pins: a core supply, vdd, and a digital input/output interface supply, vio. vio allows direct interface with any logic between 1.8 v and 5.0 v. to reduce the number of supplies needed, vio and vdd can be tied together. the ad7980 is independent of power supply sequencing between vio and vdd. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 29. figure 29. psrr vs. frequency the ad7980 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate. this makes the device ideal for low sampling rate (even of a few hz) and low battery-powered applications. figure 30. operating cu rrents vs. sampling rate digital interface though the ad7980 has a reduced number of pins, it offers flexibility in its serial interface modes. the ad7980 , when in cs mode, is compatible with spi, qspi?, and digital hosts. this interface can use either a 3-wire or 4-wire interface. a 3-wire interface using the cnv, sck, and sdo signals minimizes wiring connections useful, for instance, in isolated applications. a 4-wire interface using the sdi, cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback timing (sdi). this is useful in low jitter sampling or simultaneous sampling applications. the ad7980 , when in chain mode, provides a daisy-chain feature using the sdi input for cascading multiple adcs on a single data line similar to a shift register. the mode in which the device operates depends on the sdi level when the cnv rising edge occurs. the cs mode is selected if sdi is high, and the chain mode is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected together, the chain mode is selected. in either mode, the ad7980 offers the flexibility to optionally force a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. the busy indicator feature is enabled in the cs mode if cnv or sdi is low when the adc conversion ends (see figure 34 and figure 38). the busy indicator feature is enabled in the chain mode if sck is high during the cnv rising edge (see figure 42). 80 55 1 1000 06392-062 frequency (khz) psrr (db) 10 100 75 70 65 60 06392-055 10.000 1.000 0.100 0.010 0.001 operating currents (ma) 100000 sampling rate (sps) 10000 1000000 i vdd i vio i ref
ad7980 data sheet rev. f | page 18 of 26 3-wire cs mode without busy indicator this mode is usually used when a single ad7980 is connected to an spi-compatible digital host. the connection diagram is shown in figure 31, and the corresponding timing is given in figure 32. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. once a conversion is initiated, it continues until completion irrespective of the state of cnv. this can be useful, for instance, to bring cnv low to select other spi devices, such as analog multiplexers; however, cnv must be returned high before the minimum conversion time elapses and then held high for the maximum conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7980 enters the acquisition phase and powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate provided that it has an acceptable hold time. after the 16th sck falling edge or when cnv goes high, whichever is earlier, sdo returns to high impedance. figure 31. 3-wire cs mode without busy indicator connection diagram (sdi high) figure 32. 3-wire cs mode without busy indicator seri al interface timing (sdi high) 06392-015 ad7980 sdo sdi data in digital host convert clk vio cnv sck 06392-016 sdi = 1 t cnvh t conv t cyc cnv a quisition aquisition t acq t sck t sckl conversion sck sdo d15 d14 d13 d1 d0 t en t hsdo 123 14 1516 t dsdo t dis t sckh
data sheet ad7980 rev. f | page 19 of 26 3-wire cs mode with busy indicator this mode is usually used when a single ad7980 is connected to an spi-compatible digital host having an interrupt input. the connection diagram is shown in figure 33, and the corresponding timing is given in figure 34. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion irrespective of the state of cnv. prior to the minimum conversion time, cnv can be used to select other spi devices, such as analog multiplexers, but cnv must be returned low before the minimum conversion time elapses and then held low for the maximum conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. the ad7980 then enters the acquisition phase and powers down. the data bits are clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate provided it has an acceptable hold time. after the optional 17th sck falling edge or when cnv goes high, whichever is earlier, sdo returns to high impedance. if multiple ad7980 devices are selected at the same time, the sdo output pin handles this contention without damage or induced latch-up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. figure 33. 3-wire cs mode with busy indicator connection diagram (sdi high) figure 34. 3-wire cs mode with busy indi cator serial interface timing (sdi high) 06392-017 ad7980 sdo sdi data in irq digital host convert clk vio vio 47k? cnv sck 06392-018 t conv t cnvh t cyc aquisition aquisition t acq t sck t sckh t sckl conversion sck cnv sdi = 1 sdo d15 d14 d1 d0 t hsdo 1 2 3 15 16 17 t dsdo t dis
ad7980 data sheet rev. f | page 20 of 26 4 - wire cs mode without busy indicator this mode is usually used when multiple ad7980 devices are connected to an spi - compatible digital host. a connection diagram example using two ad7980 device s is shown in figure 35, and the corresponding timing is given in figure 36. with sdi high, a rising edge on cnv initiates a con version, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback (if sdi and cnv are low, sdo is driven low). prior to the minimum conver sion time, sdi c an be used to select other spi devices, such as analog multiplexers, but sdi must be returned high before the minimum conversion time elapses and then held high for the maximum conversion time to avoid the generation of the busy signal indi cator. when the conversion is complete, the ad7980 enters the acquisition phase and powers down. each adc result can be read by bringing its sdi input low , which consequently outputs the msb ont o sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allow s a faster reading rate provided it has an acceptable hold time. after the 16th sck falling edge or when sdi goes high, whichever is earlier, sdo returns to high impedance and another ad7980 can be read. figure 35 . 4- wire cs mode without busy indicator connection diagram figure 36 . 4- wire cs mode without busy indicator serial interface timing 06392-019 digital host convert cs2 cs1 clk data in ad7980 sdo sdi cnv sck ad7980 sdo sdi cnv sck 06392-020 t conv t cyc aquisition aquisition t acq t sck t sckh t sckl conversion sck cnv t ssdicnv t hsdicnv sdo d15 d13 d14 d1 d0 d15 d14 d1 d0 t hsdo t en 1 2 3 14 15 16 17 18 30 31 32 t dsdo t dis sdi(cs1) sdi(cs2)
data sheet ad7980 rev. f | page 21 of 26 4-wire cs mode with busy indicator this mode is usually used when a single ad7980 is connected to an spi-compatible digital host that has an interrupt input, and it is desired to keep cnv, which is used to sample the analog input, independent of the signal used to select the data reading. this requirement is particularly important in applications where low jitter on cnv is desired. the connection diagram is shown in figure 37, and the corresponding timing is given in figure 38. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback (if sdi and cnv are low, sdo is driven low). prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned low before the minimum conversion time elapses and then held low for the maximum conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the ad7980 then enters the acquisition phase and powers down. the data bits are clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate provided it has an acceptable hold time. after the optional 17th sck falling edge or sdi going high, whichever is earlier, the sdo returns to high impedance. figure 37. 4-wire cs mode with busy indi cator connection diagram figure 38. 4-wire cs mode with busy indicator serial interface timing 06392-021 ad7980 sdo sdi data in irq digital host convert cs1 clk vio 47k ? cnv sck 06392-022 t conv t cyc aquisition t ssdicnv aquisition t acq t sck t sckh t sckl conversion sdi t hsdicnv sck cnv sdo t en d15 d14 d1 d0 t hsdo 123 15 1617 t dsdo t dis
ad7980 data sheet rev. f | page 22 of 26 chain mode without busy indicator this mode can be used to da isy - chain multiple ad7980 devices on a 3 - wire serial interface. this feature is useful for reducing component count and wiring connections, for example , in isolated multi - converter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using two ad7980 s is shown in figure 39, and the corresponding t iming is given in figure 40. when sdi and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects the chain mode, and disable s the b usy indicator. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdo and the ad7980 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are clocked by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 16 n clocks are required to readback the n adcs. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allow s a faster re ading rate and, consequently , more ad7980 devices in the chain, provided the digital host has an acceptable hold time. the maximum conversion rate may be reduced due to the total readback time. figure 39 . chain mode without busy indicator connection diagram figure 40 . chain mode without busy indicator serial interface timing 06392-023 digital host convert clk data in ad7980 sdo sdi cnv a sck ad7980 sdo sdi cnv b sck 06392-024 t conv t cyc t ssdisck t sckl t sck t hsdisc t acq aquisition t ssckcnv aquisition t sckh conversion sdo a = sdi b t hsckcnv sck cnv sdi a = 0 sdo b t en d a 15 d a 14 d a 13 d b 15 d b 14 d b 13 d b 1 d b 0 d a 15 d a 14 d a 0 d a 1 d a 1 d a 0 t hsdo 1 2 3 15 16 17 14 18 30 31 32 t dsdo
data sheet ad7980 rev. f | page 23 of 26 chain mode with busy indicator this mode can also be used to daisy - chain multiple ad7980 devices on a 3 - wire serial interface while providing a busy indicator. this feature is useful for reducing component count and wiring connections, for example , in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a conn ection diagram example using three ad7980 devices is shown in figure 41, and the corresponding timing is given in figure 42. when sdi and cnv are low, sdo is driven low. with sck high, a ri sing edge on cnv initiates a conversion, selects the chain mode, and enables the busy indicator feature. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when all adcs in the chain have completed th eir conversions, the sdo pin of the adc closest to the digital host ( see the ad7980 adc labeled c in figure 41) is driven hi gh . this transition on sdo can be used as a busy indicato r to trigger the data readback controlled by the digital host. the ad7980 then enters the acquisition phase and powers down. the data bits stored in the internal shift register are clocked out, msb first, by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is cloc ked by the sck falling edge. each adc in the chain outputs its data msb first, and 16 n + 1 clocks are required to readback the n adcs. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and, consequently , more ad7980 devices i n the chain, provided the digital host has an acceptable hold time. figure 41 . chain mode with busy in dicator connection diagram figure 42 . chain mode with busy indicator serial interface timing 06392-025 ad7980 c sdo sdi data in irq digital host convert clk cnv sck ad7980 b sdo sdi cnv sck ad7980 a sdo sdi cnv sck 06392-026 t conv t cyc t ssdisck t sckh t sck t hsdisc t acq t dsdosdi t dsdosdi t dsdodsi aquisition t ssckcnv aquisition t sckl conversion t hsckcnv sck cnv = sdi a sdo a = sdi b sdo b = sdi c sdo c t en d a 15 d a 14 d a 13 d b 15 d b 14 d b 13 d c 15 d c 14 d c 13 d b 1 d b 0 d a 15 d a 14 d a 1 d a 0 d c 1 d c 0 d b 15 d b 14 d a 0 d a 1 d b 0 d b 1 d a 14 d a 15 d a 1 d a 0 t hsdo 1 2 3 15 16 17 4 18 19 31 32 33 34 35 47 48 49 t dsdo t dsdosdi t dsdosdi
ad7980 data sheet rev. f | page 24 of 26 application s information layout the printed circuit board (pcb) that houses the ad7980 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad7980 , with all its analog signals on the left side and all its digital signals on the right side, eases this task. avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the ad7980 is used as a shield. fast switching signals, such as cnv or clocks, should never run near analog signal paths. crossover of digital and analog signals should be avoided . at least one ground plane should be used. it c an be common or split between the digital and analog section. in the latter case, the planes should be joined underneath the ad7980 devices . the ad7980 voltage reference input ref has a dynamic input impedance and should be decoupled with minimal parasitic inductances. this is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the ref and gnd pin s and connect ing them with wide, low impedance traces. finally, the power supplies vdd and vio of the ad7980 should be decoupled with ceramic capacitors, typically 100 nf, placed close to the ad7980 and connected using short and wide traces to provide low impedance paths and reduce the effect of glitche s on the power supply lines. an example of a layout following these rules is shown in figure 43 and figure 44. evaluating the perfo rmance of the ad7980 other recommended layouts for the ad7980 are outlined in the documentation of the evaluation board for the ad7980 ( e va l - ad7980sdz ). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the e va l - sdp - cb1z . figure 43 . example layout of the ad7980 (top layer) figure 44 . example layout of the ad7980 (bottom layer) 06392-028 ad7980 06392-027
data sheet ad7980 rev. f | page 25 of 26 outline dimensions figure 45 .10 - lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters figure 46 . 10 - lead le ad frame chip scale package [lfcsp ] 3 mm 3 mm body and 0.75 mm package height (cp - 10 - 9) dimensions shown in millimeters contact sales for the non - rohs compliant version of the device . c o m p l i a n t t o j e d e c s t a n d a r d s m o - 1 8 7 - b a 0 9 1 7 0 9 - a 6 0 0 . 7 0 0 . 5 5 0 . 4 0 5 1 0 1 6 0 . 5 0 b s c 0 . 3 0 0 . 1 5 1 . 1 0 m a x 3 . 1 0 3 . 0 0 2 . 9 0 c o p l a n a r i t y 0 . 1 0 0 . 2 3 0 . 1 3 3 . 1 0 3 . 0 0 2 . 9 0 5 . 1 5 4 . 9 0 4 . 6 5 p i n 1 i d e n t i f i e r 1 5 m a x 0 . 9 5 0 . 8 5 0 . 7 5 0 . 1 5 0 . 0 5 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index are a sea ting plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 pin 1 indic a t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 02-05-2013-c t op view bottom view 0.20 min
ad7980 data sheet rev. f | page 26 of 26 ordering guide model 1 , 2 , 3 integral nonlinearity temperature range package description package option branding ordering quantity ad7980armz 2.5 lsb max ?40c to +125c 10 - lead msop rm -10 c5x tube, 50 AD7980ARMZRL7 2.5 lsb max ?40c to +125c 10 - lead msop rm -10 c5x reel, 1,000 ad7980brmz 1.25 lsb max ?40c to +125c 10 - lead msop rm -10 c5d tube, 50 ad7980brmzrl7 1.25 lsb max ?40c to +125c 10 - lead msop rm -10 c5d reel, 1,000 ad7980acpz -rl 2.5 lsb max ?40c to +125c 10 - lead lfcsp cp -10 -9 c5x reel, 5,000 ad7980acpz -rl7 2.5 lsb max ?40c to +125c 10 - lead lfcsp cp -10 -9 c5x reel, 1,000 ad7980bcpz -rl 1.25 lsb max ?40c to +125c 10 - lead lfcsp cp -10 -9 c5d reel, 5,000 ad7980bcpz -rl7 1.25 lsb max ?40c to +125c 10 - lead lfcsp cp -10 -9 c5d reel, 1,000 ad7980bcpz -r2 1.25 lsb max ?40c to +125c 10 - lead lfcsp cp -10 -9 c5d reel, 1,000 eval - ad7980sdz evaluation board eval - sdp - cb1z controller board 1 z = rohs compliant part. 2 the eval - ad7980sdz can be used as a standalone evaluation board or in conjunction with the eval - sdp - cb1z for evaluation/demonstration purposes. 3 th e eval - sdp - cb1z allows a pc to control and communicate with all analog devices evaluation boards ending in the sd designator. ? 2007 C 2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06392 - 0- 10/17(f)

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